1. Field of the Invention
The present invention relates to packaging substrates, and more particularly, to a packaging substrate and a fabrication method thereof for improving the product reliability.
2. Description of Related Art
Along with the rapid development of electronic industries, electronic products are developed toward the trend of multi-function and high performance. To improve the wiring precision of multi-layer circuit boards, redistribution layer (RDL) technologies have been developed to alternately stack a plurality of dielectric layers and circuit layers on one another and form a plurality of conductive vias in the dielectric layers to electrically connect upper and lower circuit layers. Further, coreless packaging technologies have been developed to meet the miniaturization requirement.
FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a packaging substrate 1 according to the prior art.
Referring to FIG. 1A, a carrier 10 is provided and a conductive layer 100 is formed on upper and lower sides of the carrier 10.
Referring to FIG. 1B, a first circuit layer 11 is formed on the conductive layer 100 by electroplating. The first circuit layer 11 has a plurality of first conductive pads 110.
Referring to FIG. 1C, a dielectric layer 12 is formed on the carrier 10 and the first circuit layer 11.
Referring to FIG. 1D, a second circuit layer 13 is formed on the dielectric layer 12. The second circuit layer 13 has a plurality of second conductive pads 130. Further, a plurality of conductive vias 14 are formed in the dielectric layer 12 for electrically connecting the first circuit layer 11 and the second circuit layer 13.
Referring to FIG. 1E, the carrier 10 is removed to expose the conductive layer 100.
Referring to FIG. 1F, the conductive layer 100 is removed to expose the first circuit layer 11. Then, a first solder mask layer 15 is formed on an upper side of the dielectric layer 12 and the first circuit layer 11 and a plurality of first openings 150 are formed in the first solder mask layer 15 so as to expose the first conductive pads 110 and portions of the dielectric layer 12 around peripheries of the first conductive pads 110, and a second solder mask layer 16 is formed on a lower side of the dielectric layer 12 and the second circuit layer 13 and a plurality of second openings 160 are formed in the second solder mask layer 16 to expose the second conductive pads 130.
Subsequently, referring to FIG. 1G, an electronic element 9 is disposed on the first conductive pads 110 through a plurality of conductive elements 18 made of such as a solder material. That is, the conductive elements 18 come into contact with surfaces 110a of the first conductive pads 110. However, such planar contact surfaces lead to small contact area between the conductive elements 18 and the first conductive pads 110, thus adversely affecting the bonding strength between the conductive elements 18 and the first conductive pads 110 and easily causing delamination of the conductive elements 18 from the first conductive pads 110. Therefore, the product reliability is reduced.
In an embodiment, after the carrier 10 is removed, the first circuit layer 11 is etched to have a surface lower than that of the dielectric layer 12. That is, the first circuit layer 11 is recessed into the dielectric layer 12 about 5 um, which however easily causes non-wetting of the conductive elements 18 and consequently causes the conductive elements 18 to be stuck on the surface of the dielectric layer 12 without electrically connecting to the first conductive pads 110.
Therefore, there is a need to provide a packaging substrate and a fabrication method thereof so as to overcome the above-described drawbacks.